1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Related Prior Art
A semiconductor memory device chiefly operates on a method of accumulating electric charges in a capacitor formed in the semiconductor device, and storing the data depending on the presence or absence of electric charge (generally called dynamic random access memory or DRAM). In this capacitor, a silicon oxide film is generally used as an insulation film.
Recently is devised, by using a ferrodielectric material as this insulation film, a semiconductor memory device for making nonvolatile the data to be stored.
A conventional semiconductor memory using Ferroelectric material is described below while referring to U.S. Pat. No. 4,873,664.
FIG. 24 is a circuit diagram of a conventional semiconductor memory device, FIG. 25 is an operation timing chart of the semiconductor memory device of FIG. 24, FIG. 26 is a diagram showing the hysteresis characteristic of Ferroelectric element used in the main body cell capacitor in the conventional semiconductor memory device of FIG. 26, and FIG. 27 is a diagram showing the hysteresis characteristic of the Ferroelectric element used in a dummy cell capacitor in the conventional semiconductor memory device.
In the circuit configuration of the conventional semi-conductor memory device in FIG. 24, bit lines 26, 28 are connected to a sense amplifier 30. Main body memory cells 20a, 20b, 20c and 20d, 20e, and dummy memory cells 46 and 36 are connected to the bit lines 26 and 28, respectively. The main body memory cell 20a is composed of a MOS transistor 24 and a main body memory cell capacitor 22. The gate of the MOS transistor 24 is connected to a word line 32, the drain of the MOS transistor 24 is connected to the bit line 26, and the source of the MOS transistor 24 is connected to a first electrode of the main body memory cell capacitor 22. A second electrode of the main body memory cell capacitor 22 is connected to a cell plate electrode 84. Similarly, the dummy memory cell 86 is composed of a MOS transistor 88 and a dummy memory cell capacitor 40. The gate of the MOS transistor 88 is connected to a dummy word line 42, the drain of the MOS transistor 88 is connected to the bit line 28, and the source of the MOS transistor 88 is connected to a first electrode of the dummy memory cell capacitor 40. A second electrode of the dummy memory cell capacitor 40 is connected to a dummy cell plate electrode 44.
The operation of this conventional semiconductor memory cell device is explained below by reference to the operation timing chart in FIG. 25, the hysteresis characteristic diagram of the Ferroelectric element of the main body memory cell capacitor in FIG. 26, and the hysteresis characteristic diagram of the Ferroelectric element of the dummy memory cell capacitor in FIG. 27.
FIG. 26 and FIG. 27 are the hysteresis characteristic diagrams of the Ferroelectric element. The axis of abscissas denotes the electric force applied to the memory cell capacitor, and the axis of ordinates represents the electric charge at that time. As shown in FIG. 26 and FIG. 27, in the Ferroelectric capacitor, if the electric force is 0, the residual polarization is left over as indicated at point B, point E, point K, and point H. After turning off the power source, too, a residual polarization occurs in the Ferroelectric capacitor. By making use thereof to obtain nonvolatile data, a nonvolatile semiconductor memory device is realized. The main body memory cell capacity is in the state of point B in FIG. 26 when the memory cell data is 1, and in the state of point E in FIG. 26 when the memory cell data is 0. The initial state of the dummy memory cell capacitor is the state of point K in FIG. 27. Herein, to read out the data in the main body memory cell, as initial state, the logic voltages of the bit lines 26 and 28, word line 32, dummy word line 42, cell plate electrode 34, and dummy cell plate electrode 44 are set to L. Later, the bit lines 26 and 28 are set in floating state.
Next, as shown in FIG. 25, the word line 32, dummy word line 42, cell plate electrode 34, and dummy cell plate 44 are all set to logic voltage H. As a result, the MOS transistors 24 and 38 are turned on, and electric force is applied to the main body memory cell capacitor 22 and dummy memory cell capacitor 40. At this time, if the data of the main body memory cell is 1, the state at point B in FIG. 26 is changed to the state at point D, and an electric charge Q1 is read out in the bit line 26. If the data of the main body memory cell is 0, the state at point E in FIG. 26 is changed to the state at point D, and an electric charge Q0 is read out in the bit line 26. The dummy memory cell changes from the state at point K in FIG. 27 to the state at point J, and an electric charge Qd is read out in the bit line 28. The data of the main body memory cell read out in the bit line 26 and the data of the dummy memory cell read out in the bit line 28 are amplified by the sense amplifier 30, and the data in the main body memory cell are read out.
When the data of the main body memory cell is 1, the bit line 26 is at logic voltage H, and the cell plate electrode 34 is at logic voltage H. Accordingly, electric force is not applied to the main body memory cell capacitor 22, thereby coming in the state at point E in FIG. 26. Afterwards, to return the state of the data of the main body memory cell capacitor 22 to the state at point B in FIG. 26, the logic voltage of the cell plate electrode 34 is set to L, and is once to set the state at point A in FIG. 26, and the logic voltage of the word line 32 is set to L. When the word line 82 is at logic voltage L, electric force is not applied to the main body memory cell capacitor 22, thereby returning to the state at point B in FIG. 26.
Likewise, when the data of the main body memory cell is 0, the bit line 26 comes to the logic voltage L, and the cell plate electrode 34 comes to the logic voltage H. Accordingly, the main body memory cell capacitor 22 is in the state of point D in FIG. 26. When the cell plate electrode 34 is at logic voltage L, electric force is not applied to the main body memory cell capacitor 22, thereby coming to the state of point E in FIG. 26. Afterwards, the logic voltage of the word line 32 comes at L, and electric force is not applied yet to the main body memory cell capacitor 22, thereby remaining at the state of point E in FIG. 26.
In the dummy memory cell, when the main body memory cell data is 1, the bit line 28 is at the logic voltage L, and the cell plate electrode 44 is at the logic voltage H. Accordingly, the dummy memory cell capacitor 40 is in the state of point J in FIG. 27. Later, when the dummy word line 36 is at the logic voltage L, electric force is not applied to the dummy memory cell capacitor 40, thereby returning to the state of point K in FIG. 27.
Similarly, when the data of the main body memory cell is 0, the bit line 28 is at the logic voltage H, and the cell plate electrode 44 is at the logic voltage H. Accordingly, the dummy memory cell capacitor 40 is in the state at point K in FIG. 27. When the dummy word line 36 is later set to the logic voltage L, if the logic voltage of the dummy cell plate electrode 44 is set to L at the same time, the state of no application of electric force in the dummy cell memory capacitor 40 is unchanged, and the state at point K in FIG. 27 is maintained.
However, in the semiconductor memory device of the conventional constitution and operation as shown above, as the initial state right after manufacturing process, the dummy memory cell capacitor does not always become state of point K in FIG. 27. Hence, if the initial state is the state of point H in FIG. 27, the problem was that malfunction occurred in the first reading.
In the conventional semiconductor memory device, after reading out the data, and amplifying the electric charge being read out in the bit line by the sense amplifier, the dummy word line 42 and dummy cell plate electrode 44 are simultaneously set to the logic voltage L. Therefore, for example, if the parasitic capacity of the dummy word line 42 is large and the fall of the dummy word line 42 is later than the fall of the dummy cell plate electrode, at the time of "0" of the data of the main body memory cell, the bit line 28 comes to the logic voltage H, and the cell plate electrode 44 comes to the logic voltage L. Hence, the dummy memory cell capacitor 40 comes to the state of point G in FIG. 27. As the dummy word line 42 is later set to the logic voltage L, the dummy memory cell capacitor 40 comes to the state of point H in FIG. 27. Thus, unless the dummy memory cell capacitor 40 is in the state at point K in FIG. 27 which is the initial state, the problem was that malfunction occurred at the next time of reading out the memory cell.
Another problem was that the data was read out in the bit line very late because the cell plate electrode was raised after raising the word line when reading out the data of the memory cell.
Besides, the rise of word line and dummy word line, and that of cell plate electrode and dummy cell plate, were simultaneous, and the fall of word line and dummy word line and that of dummy cell plate were simultaneous, and hence much electric power was consumed for driving them.